DARPA Chooses Teams for $1.5 Billion Electronics Initiative
The Defense Advanced Research Projects Agency has chosen a multitude of industry and academic teams to work on six programs under its lucrative Electronics Resurgence Initiative that includes upwards of $1.5 billion in funding over five years, an official announced.
The initiative — which was revealed last year — is meant to jumpstart innovation in the electronics industry. The technology underpins some of the Defense Department’s top technology focus areas including quantum computing, artificial intelligence, advanced manufacturing, space and biotechnology, Pentagon officials have said.
The effort comes at a time when the cost of doing business in the sector is skyrocketing and foreign countries are making greater investments, said Bill Chappell, director of DARPA’s microsystems technology office.
“We are at this really interesting point in time and DARPA decided that … we would have an increased concentration on the basics of electronics and the basics of semiconductors,” he told reporters during a teleconference three days prior to a major meeting between the agency and its industry and academic partners in San Francisco known as the ERI Summit.
The event — which takes place between July 22 and July 24 — includes more than 950 participants, Chappell said. It will include discussions about the future of electronics, particularly as it relates to Moore’s Law, a theory that says integrated circuits will double in capacity every 18 months to two years.
“DARPA has had a long history in sponsoring research that propels that forward,” he said. “We’ve had an exponential rise in capability.”
Through targeted investments, the agency plans to foster foundational enhancements within the industry that are beyond what any corporate partner would do on their own, Chappell said.
The ERI effort includes six programs under three pillars — architectures, design and materials and integration. The software-defined hardware (SDH) and domain-specific system-on-chip (DSSoC) programs are under architectures. The intelligent design of electronic assets (IDEA) and posh open source hardware (POSH) programs are under design. The three-dimensional monolithic system-on-a-chip (3DSoC) and foundations required for novel compute (FRANC) programs are under materials and integration.
During the summit DARPA announced that it had selected numerous companies and universities to participate in the ERI programs.
Intel, NVIDIA, Qualcomm, Systems & Technology Research, the Georgia Institute of Technology, Stanford University, University of Michigan, University of Washington and Princeton University were selected for the SDH program. The effort “aims to develop hardware and software that can be reconfigured in real time based on the data being processed, adapting the computing architecture for the workload and data at hand,” according to DARPA.
IBM, Oak Ridge National Labs, Arizona State University and Stanford University were chosen for the DSSoC program, which is meant to “enable the rapid development of multi-application systems through a single programmable framework,” according to the agency.
The University of California at San Diego, Northrop Grumman Mission Systems, Cadence Design Systems, Xilinx, Inc., Synopsys, Inc., University of Southern California, Princeton University and Sandia National Laboratories were selected for the IDEA and POSH programs. IDEA is meant to create a “no human-in-the-loop” layout generator that can enable users with limited electronic design experience to quickly create the physical design of an electronic hardware system, the agency said. POSH is meant “to create an ethos of sharing in the hardware community that is similar to what the software community uses,” Chappell said. This will be done by standing up a foundation of verified IP building blocks with known functionality, according to DARPA.
The Georgia Institute of Technology and a second team with researchers from Stanford University, Massachusetts Institute of Technology and Skywater Technology Foundry were chosen for the 3DSoC program.
“The 3DSoC program aims to develop materials, design tools and fabrication techniques for building microsystems on a single substrate with a third dimension,” according to DARPA.
HRL Laboratories, Applied Materials, Ferric, Inc., the University of California at Los Angeles, University of Minnesota and University of Illinois at Urbana-Champaign have been tapped for the FRANC program. That is meant to foster the “design of circuits that leverage the properties of new materials and integration schemes to process data in ways that eliminate or minimize data movement,” the agency said.
DARPA’s investment in microelectronics comes at a time of increased competition between the United States and China. In the 2018 national defense strategy, the Pentagon described Beijing as one of its two great power competitors moving forward. The eastern nation has made it a point to increase its investment in microelectronics, setting aside $150 billion in funding.
China’s investment is particularly worrisome because the Pentagon fears that the country could hide malicious apps or code inside U.S. military systems that use their chips.
Chappell noted that much of China’s investment is going toward manufacturing facilities rather than attempting to make advancements in the technology.
“But it does underscore the need to make sure that we have new inventions occurring across our country and other allied countries where we invent new processes as older processes are being replicated en masse,” he said. “It’s more important than ever that we have new inventions that are coming out of the pipeline to make sure that the semiconductor space does not become a commodity.”